Search - pipeline verilog

[Other] statemachine11.2

Description: 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
Platform: | Size: 1854 | Author: 陶玉辉 | Hits:

[Other resource] pipe

Description: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
Platform: | Size: 5356 | Author: 刘陆陆 | Hits:

[Program doc] firfilter14

Description: 用Quartus II实现综合布线，要求充分利用Altera Stratix/Stratix II的器件的DSPBLOCK资源，Quartus II综合出的系统最高工作频率达到270Mhz以上.用Verilog进行编程。-Pipeline FIR structure。
Platform: | Size: 2048 | Author: 卢大成 | Hits:

[VHDL-FPGA-Verilog] adder16_2

Description: 16位2级流水线加法器的Verilog设计-16 2 pipeline adder Verilog Design
Platform: | Size: 1024 | Author: xiaobai | Hits:

[VHDL-FPGA-Verilog] gcd_performence

Description: 基于流水线设计的性能优先的gcd算法的verilog 代码频率可达500M-based pipeline design gcd for high clock
Platform: | Size: 3072 | Author: youyou | Hits:

[VHDL-FPGA-Verilog] DataMemory

Description: datamemory code in verilog for pipeline processor
Platform: | Size: 1024 | Author: kallu | Hits:

[Program doc] berckley pipeline adc verilog model

Description: berckley pipeline adc verilog model
Platform: | Size: 1457664 | Author: beidawuxi123 | Hits:

[VHDL-FPGA-Verilog] DLX-pipeline-in-verilog

Description: verilog实现DLX指令集5段流水线-5 stage DLX pipeline implemented in verilog
Platform: | Size: 915456 | Author: 陈祥 | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_5_10

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 4096 | Author: GTONJu | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_8_23

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 6144 | Author: theCPI | Hits:

[VHDL-FPGA-Verilog] 8-point-pipeline-fft-by-verilog.pdf

Description: 简单的8位基2 流水 fft verilog-Simple 8 base 2 pipelined fft verilog
Platform: | Size: 220160 | Author: 张涛 | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_5_10

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 4096 | Author: 行唐县城 | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_8_23

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 6144 | Author: anmili | Hits:

[VHDL-FPGA-Verilog] pipeline

Description: 使用VERILOG實現MIPS2000的PIPELINE-Use VERILOG realized MIPS2000 the PIPELINE
Platform: | Size: 2048 | Author: opgp | Hits:

[VHDL-FPGA-Verilog] pipeline

Description: 简单的流水线的实现机制，基于verilog语言。-The pipelined implementation, based on Verilog language.
Platform: | Size: 1024 | Author: mxc | Hits:

[VHDL-FPGA-Verilog] Cordic-arithmetic-pipeline

Description: FPGA实现基于Cordic算法的流水线结构设计，相关verilog语言代码-FPGA to realize the Cordic code
Platform: | Size: 229376 | Author: 孙永林 | Hits:

[VHDL-FPGA-Verilog] CPU_Verilog

Description: 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
Platform: | Size: 12288 | Author: fairchildfzc | Hits:

[VHDL-FPGA-Verilog] highperformance

Description: 最大公约数（GCD）stein算法实现，高性能流水线实现(The greatest common divisor (GCD) stein algorithm, high performance pipeline implementation.)
Platform: | Size: 2048 | Author: BetaGo | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: Booth乘法器是属于位操作乘法器，采用流水线结构实现(The Booth multiplier is a bit-operated multiplier that is implemented in a pipeline structure.)
Platform: | Size: 2138112 | Author: wlkid1412 | Hits:

[Other] 1

Description: 针对矿浆管道工况调整给泄漏检测带来的干扰，准确提取泄漏信号的特征量是降低泄漏误报、漏报的关键。为此，提出了一种基于经验模态分解（EMD）、Hilbert能量谱与变量预测模型（VPMCD）相结合的泄漏检测方法。该方法首先将压力信号分解成若干个固有模态函数（IMF）之和，然后将IMF分量进行Hilbert变换得到局部Hilbert能量谱，依据能量分布的标准差选择最能准确反映矿浆管道运行工况的局部能量谱作为特征值向量，最后通过VPMCD分类器建立泄漏识别模型。将该方法应用于泄漏检测中，实验结果表明，矿浆管道在正常运行、泄漏和工况调整状态下，识别率达到95%，并综合分析流量信号，提高了泄漏检测精度。(According to the interference to leak detection of mineral slurry pipeline caused by work condition adjustment,effectively extracting the characteristics of leak signal is the key to reduce the leakage of the false negatives and false positives.In this paper,a leak detection method based on EMD and VPMCD is proposed. In this method,the pressure signals are decomposed into several IMF components, and then take local Hilbert energy spectrum which most accurately reflect the pipeline operation conditions as feature values, Finally the leak identification model is established by VPMCD classifier.When the method is applied to the leak detection,the experimental results show that under the conditions of normal operation,leakage and work condition adjustment, the recognition rate of the mineral slurry pipeline reaches 95%,and by comprehensively analyzing the flow signals, it also improves the accuracy of leak detection.)
Platform: | Size: 4096 | Author: M-min | Hits:

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[Other] statemachine11.2

[Other resource] pipe

[Program doc] firfilter14

[VHDL-FPGA-Verilog] adder16_2

[VHDL-FPGA-Verilog] gcd_performence

[VHDL-FPGA-Verilog] DataMemory

[Program doc] berckley pipeline adc verilog model

[VHDL-FPGA-Verilog] DLX-pipeline-in-verilog

[Embeded-SCM Develop] cf_fp_mul_p_5_10

[Embeded-SCM Develop] cf_fp_mul_p_8_23

[VHDL-FPGA-Verilog] 8-point-pipeline-fft-by-verilog.pdf

[Embeded-SCM Develop] cf_fp_mul_p_5_10

[Embeded-SCM Develop] cf_fp_mul_p_8_23

[VHDL-FPGA-Verilog] pipeline

[VHDL-FPGA-Verilog] pipeline

[VHDL-FPGA-Verilog] Cordic-arithmetic-pipeline

[VHDL-FPGA-Verilog] CPU_Verilog

[VHDL-FPGA-Verilog] highperformance

[VHDL-FPGA-Verilog] multiplier

[Other] 1

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